” 写作RV64I ISS编程、 写作C/C++程序语言Computer ArchitectureAssignment RISC-V RV64I ISS Stage 1Your task for this assignment is to develop an instruction set simulator (ISS) for the RV64I subset of the RISC-Vinstruction set. An instruction set simulator is a program used by computer architects to simulate execution of acomputers instructions. It contains representations of the computers memory and the internal registers of the CPU.It responds to commands that specify initialization and inspection of the memories and registers, and controlexecution of instructions.The RISC-V instruction Set is described in The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA, availableon the course web site. The RV64I subset is described in Chapter 5 of the Instruction Set Manual, building on theRV32I subset described in Chapter 2. The instruction encoding is summarized in Chapter 24. For this assignment,you should implement just the RV64I base integer instruction set, with the following exceptions: FENCE: This instruction should be decoded as a legal instruction, but perform no operation. ECALL, EBREAK: These instructions should be decoded as legal instructions, but a message should bedisplayed indicating they are unimplemented.For load and store instructions, you can assume that the effective address is properly aligned. Do not implement misalignedloads or stores. For any fetched instruction word that Does not represent an RV64I instruction, a messageshould be displayed indicating the instruction is illegal. In Stage 2, you will implement exception handling, whichwill be used for illegal instructions.We have provided a skeleton program on the course Web site for you to use as a starting point. The program is writtenin C++, and islocated in the Assignment file Folder (also linked in the Assignment module). You can download eitherrv64sim.zip or rv64sim.tgz; the content is the same in each. The skeleton program implements processing of command-lineoptions and input commands. Your task isto implement classesto model the processor and memory. Headerfiles are provided showing the member functions required. You can add additional classes if you need to.The only command-line option you need to implement at this stage is the -v option to enable verbose output. If the -v option is specified on the command line, your program can display debugging information. If the option is omitted,your program should display only the output required for each command. Your program must format that outputexactly as specified below, since the assessment process will compare you output with expected output.The rv64sim program reads commands from the standard input stream, one command per line. The commands are:Command Operation performedxn Show the content of register xn in hex (n is register number, from 0 to 31). The value isdisplayed as 16 hex digits with leading 0s.xn = value Set register xn to value (value in hex).pc Show content of PC register in hex. The value is displayed as 16 hex digits with leading0s.pc = address Set PC register to Address (address in hex).m address Show the content of memory doubleword at address (address in hex, rv64sim rounds itdown to nearest doubleword-aligned address). The value is displayed as 16 hex digitswith leading 0s.m address = value Set memory doubleword at address to value (address in hex, rv64sim rounds it down tonearest doubleword-aligned address; value in hex).l filename Load memory from Intel hex format file named filename. If the file includes astart address record, the PC is set to the start address.. Execute one instruction.2Command Operation performed. n Execute n instructions.b address Set an execution Breakpoint at address. If the simulator is executing multipleinstructions (. n command), it stops when the PC reaches address without executing thatinstruction. There is only one execution breakpoint; using the b command with adifferent address removes any previously set breakpoint.b Clear the breakpoint.Each command may be followed by a comment, starting with the # character and extending to the end of the line.Blank lines are permitted, as are lines containing only a comment.The initial value of all processor general purpose registers should be 0, and the initial value of the PC should also be0. The memory should appear to have all locations initialized to 0. Your program should count the number ofinstructions executed. This will be reported on completion of execution.You can test your ISS by using the m command to set memory locations to the encoded value of RISC-Vinstructions, using the pc command to set the PC to the start of the code, then using the . command to executethe code. Alternatively, you can use the RISC-V GNU Compiler Toolchain (C compiler, assembler, linker, binutils;available at httpss://github.com/riscv/riscv-gnu-toolchain) to generate hex files to load into memory. We will useboth of these processes when we assess your ISS.Performance of an ISS program is important. Computer architects typically use them to develop code for embeddedsystem, so they must be able to execute 100s of thousands of instructions per second. You should design your ISSwith performance in mind. The skeleton program provided uses the native integer data types uint32_t and uint64_t torepresent instructions and data, rather than using a dynamically allocated class-typed object or string. When youimplement the memory, you should not attempt to represent it using a large array of words. Since addresses are 64bits, that would imply an array of 264 bytes. Instead, consider a representation that allocates blocks of memory ondemand (that is, on the first read or write to an address within a block).Please keep an eye on the Questions and Answers forum on the course web site. There will no doubt be questions ofclarification of requirements arising that we will answer there. We will also announce incremental releases of a testsuite that you should use to test your program.You must develop your program and check it into a Subdirectory named 20xx/s1/ca/rv64sim in your SVN repository(xx represents the last 2 digits of the year). We will provide a web submission script that will check out thissubdirectory, make your ISS, and run it with several test cases. Compliance with this development process willcount toward the assessment of the Assignment. The script will compare your output with our expected output usingthe diff -iw command (differences ignoring case and white-space).Your work for Stage 1 will be assessed in the web submission system based on the following criteria, with pointsawarded out of 1500: Program builds and runs using web submission script 100 points Correct execution of instruction, based on the number of test cases that pass 1300 points Program efficiency, based on run time not exceeding a limit 100 pointsThe points for this assignment will comprise 15% of your final assessment for the course.For the submission deadline, please refer to the course page on MyUni.3Postgraduate requirementsIf you are enrolled in the postgraduate course (COMP SCI 7026), you should implement the following additionalrequirements:During simulated execution, you should count the number of simulated clock cycles, in addition to the number ofinstructions executed. You should use the following cycle counts for various instruction types: Conditional branch instruction: 2 cycles if the branch is taken, or 1 cycle if the branch is not taken. Unconditional branch instruction: 2 cycles. Load instruction: 3 cycles. Store instruction: 2 cycles. All other instructions: 1 cycle.On completion of a simulation, if the -c Option is specified on the command line, your program will report the totalnumber of simulated clock cycles taken.请加QQ：99515681 或邮箱：99515681@qq.com WX：codehelp
“
添加老师微信回复‘’官网 辅导‘’获取专业老师帮助，或点击联系老师1对1在线指导。
