ECE 510编程辅导、写作C++程序设计

” ECE 510编程辅导、写作C++程序设计ECE 510: Foundations of Computer EngineeringProject 3MIPS SimulatorThis assignment will give you experience in programming in C++ and the operation of a MIPSpipelined processor. Further, you will gain insight into how multiple events that occur in parallelcan be simulated using a sequential machine.1. Problem StatementThis assignment Requires a simple 5 stage pipelined machine to be simulated. The simulatorshould be capable of implementing the MIPS architecture on a cycle by cycle basis. The simulatormust be cycle accurate with respect to contents of the registers, but need not be faithful to otherhardware details such as control signals. The output of the simulator, in addition to the registercontents and latch Values should include the utilization factor of each functional unit and thetotal time in cycles to Execute a set of instructions. Implement the simulator according to thespecifications described below in C++. Submit the code, simulation results and a projectdescription write-up.1.1 Instructions to be implementedThe simulator should implement the following instructions: add, sub, addi, mul, lw, sw, beq, lui,and, andi, or, ori, sll, srl, slti, and sltiu. Note that these instructions operate integer instructionsonly. The MIPS instruction format can be used for all instructions except mul. Assume the syntaxfor mul is mul $a,$b,$c, meaning that we multiply the contents of $b and $c, the least significant32 bits of results are placed in register $a and the most significant 32-bits of the result will bestored in register $(a+1). For example, mul $t0, $t8, $t9 will store lower 32-bits of the product of$t8 * $t9 in register $t0 and the upper 32-bits of the product in register $t1 (Hint: See MIPS greensheet instructions Summary for registers numbering). This is different from the mult instructionin MIPS. Assume the opcode and function code for mul to be same as that of mult.1.2 Inputs to the simulator1) MIPS machine code as a text file: Convert the assembly level instructions to machine level byusing httpss://www.eg.bucknell.edu/~csci320/mips_web/ or https://www.kurtm.net/mipsasm/2) A query to the user to select between instruction or cycle mode Instruction mode: To observe execution of the program instruction by instruction Cycle mode: To observe execution of the program cycle by cycle3) A query to the user to select the number of instructions or cycles (depending on the choicemade in the previous query) to be executed.4) After executing the number of instructions or cycles entered initially by the user, a thirdquery to the user to choose to continue execution or not. If yes, Repeat from step 3 If no, exit the execution and display the results1.3 Memory, Registers and PCThe memory is one word wide and 2K bytes in size. There are physically separate instruction anddata memories for the instruction and data. Data memory is initialized to 0 at the beginning ofeach simulation run. There is no cache in this machine.There are 32 registers; Register 0 is hardwired to 0. In addition, there is a Program Counter (PC).PC should start execution by fetching the instruction stored in the location to which it isinitialized.1.4 CPUThe pipelined MIPS processor has 5 stages: IF, ID, EX, MEM, WB. There are pipeline registersbetween the stages: IF/ID, ID/EX, EX/MEM, MEM/WB. Assume the pipeline registers to containfollowing latches: IF/ID : IR, NPC ID/EX : IR, NPC, A, B , Imm EX/MEM : IR, B, ALUOutput , cond MEM/WB : IR, ALUOutput, LMD1.5 Output of the simulatorIn addition to displaying the register contents and latch values after the execution of eachcycle/instruction, it should output the following statistics Utilization of each stage. Utilization is the fraction of cycles for which the stage isdoing useful work. Just waiting for a structural, control, or data hazard to clear infront of it does not constitute useful work. Total time (in CPU cycles) taken to execute the MIPS program on the simulatedmachine. (This is NOT the time taken to execute the simulation; it is the timetaken by the machine being simulated.)1.6 Dealing with branchesThe processor does not implement branch prediction. When the ID stage detects a branch, it asksthe IF stage to stop Fetching and flushes the IF_ID latch (inserts NOP). When the EX stage resolvesthe branch, IF is allowed to resume instruction fetch depending on the branch outcome.1.7 Other remarks No interrupts. Does not support out of order execution Does not support data forwarding Assume register writes are completed in the first half of clock cycle and register readsare carried out in the second half. All data, structural and control hazards must be taken into account. Branches are resolved in the EX stage.2. Way to approach (Suggestion)Start by figuring out how to Implement the Pipeline registers (use of class is recommended), the5 stages of the pipeline, instruction and data memory, 32 registers and PC. Think of how theexecution of 5 stages of the pipeline (which is a parallel operation) could be done in C++ (whereinstructions are executed sequentially). Figure out a way to account for data, structural andcontrol hazards. Finally think of How the utilization and total time to execute the program can bemeasured.请加QQ：99515681 或邮箱：99515681@qq.com WX：codehelp

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