” BBU4202程序 写作、 写作Java，c/c++程序Digital Circuit Design Course Code: BBU4202 Electronic Engineering DepartmentLab Sheet 2: Logic Design using VHDL Date: ___________________________Students Surname, First Name (in English):____________________________________________ Students BUPT Number, Class Number: ________________________________Email Username (ee11bxxx):____________________________________________ Total Mark (out of 50):________________________________IMPORTANT:(a)In advance of the lab session: Print this Lab Sheet, read it and complete all the indicated Preparatory Work.(b)Write all your answers on this Lab Sheet, where indicated.(c)Use additional A4 sheets of paper if you require more space to Write your answers, ensuring that the question numbers are indicated clearly.(d)Before handing in your Lab Sheet, make sure that you fill in the Table above with your personal details, and staple any additional answer sheets (with your name written on them) together with this Lab Sheet.1.Learning Objectives Preparatory WorkBBU4202作业 写作、 写作Java，c/c++，Python程序语言作业、 辅导data作业The aims of this Lab Session Are to learn how to use VHDL to design and simulate some basic logic circuits, namely: a NAND gate and three types of Adders (Half, Full and Parallel).2.VHDL Experiments2.1. Create the Combinational CircuitsUsing VHDL， design an 8-3 Priority Encoder/3-8 Decoder/8-1 Multiplexer. （Choose 1）VHDL codeWrite below the VHDL code!2.2. Create the Test Bench and give simulation2.3. Create the Sequential CircuitsUsing VHDL， design an Modulo-10 Counter with synchronous setload enable.VHDL codeWrite below the VHDL code2.4. Create the Test Bench and give simulation如有需要，请加QQ：99515681 或邮箱：99515681@qq.com
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