写作COMPSYS201编程、Python，Java，c/c++编程

” 写作COMPSYS201编程、Python，Java，c/c++编程University of Auckland Lab 3 COMPSYS201 – 20201 | P a g eLab 3: Simple Calculator Register Transfer Level Design withDatapath + Finite State Machine (FSM) based Control Unit(3%)BackgroundThis simple calculator can perform three different operations: addition,subtraction, and multiplication of two positive decimal numbers, where eachnumber can be up to two decimal digits (i.e. 00 to 99).The actual hardware implementation uses some simple but common interfaces: a4x4 matrix keypad for entering inputs into the FPGA chip and four 7-segmentdisplays for displaying outputs from the chip. The conceptual illustration of thecalculator is presented in Figure 1.Calculator (FPGA) Calculator (FPGA) 44. Figure 1: Calculator and its inputs/outputsThe 4×4 matrix keypad consists of 16 keys. Keys 0 to 9 on the keypad are usedfor entering decimal digits, and keys A to F are used to set the different operationsas detailed in Table 1.Table 1: Calculator key representationsKey OperationA Calculator ON key, performs global reset (emulates power-ON function)B Execute key, performs equal (=) operationC Clear key, clears current result and reinitialises all registers of the calculator to 0D Multiply key, performs multiplication on the two input operandsE Subtract key, performs subtraction on the two input operandsF Add key, performs addition on the two input operandsAfter the calculator is designed and implemented on the DE0 FPGA board, a usershould press key A, which mimics power-ON and initialises the calculator to aknown initial state. The same key can be used at any stage to mimic the powerONoperation. By pressing key A, all internal registers of the calculator areinitialised to zero (i.e. reset).University of Auckland Lab 3 COMPSYS201 – 20202 | P a g eCalculator design spefificationsThe user can then enter a positive decimal number of up to two digits (numbersfrom 0 to 99) by pressing the number keys (0 to 9) one after another. Individualdigits are represented with their binary 4-bit codes (BCD). All entered numbersare considered positive. The entered digits will be displayed on the 7-segmentdisplays, so the user knows which number was entered during this step.The entered digits are internally stored in a shift register (Reg_A) that receives 4bits (i.e. one decimal digit) at a time and always stores the last two entered digits;all previously entered digits will be overwritten. These two digits represent thefirst operand (operandA).After entering the first operand, the user can press one of the operation keys: Dfor multiplication, E for subtraction or F for addition operation. The 4-bit binarycode of the operation will be stored in the Reg_OP register.After specifying the operation, the second operand (operandB) can be entered anddisplayed on the 7-segment display in the same way as the first operand. Thisoperand will be stored internally in a shift register (Reg_B).Once both operands and the operation are entered, the user can press key B toperform the actual operation. The result is stored in a result register (Reg_R) anddisplayed on the 7-segment display. If the user then wants to perform anotheroperation on a new set of operands, key C should be pressed to clear all internalregisters and 7-segment displays.Based on these specifications, we can be certain that the range of input values arefrom 0 to 99 and the range of output values are from 0 to 9801 (99×99), whichcan be displayed on four 7-segment display. (Assuming that operandA is alwaysbigger than operandB, so no negative number will be produced as the output ofthe calculator.)To design this simple calculator, you can assume that you have the followingcomponents made available to you:1. Shift register: The provided shift register is 8-bit wide (i.e. can store two4-bit digits). It has a reset and load_enable control input, and 4-bit datainput. When reset input is set to 1, the shift register content will be clearedto zero. When load_enable input is 1, the number stored in the leastsignificant 4-bit will be transferred to the most significant 4-bit locations,and the 4-bit input data will be stored into the least significant 4-bitlocations.2. Register: The provided register is either 4-bit wide (for storing operation)or 16-bit wide (for storing result). The register has load_enable controlinput. When load_enable is 1, the input data will be stored in the register.3. Arithmetic unit: The provided arithmetic unit can perform addition,subtraction and multiplication according to a 4-bit binary code of theoperation, op_sel, where 1111 is for addition, 1110 is for subtraction, and1101 is for multiplication.4. Multiplexer: The provided multiplexer selects which number to bedisplayed on the output interface (i.e. the 7-segment displays). TheUniversity of Auckland Lab 3 COMPSYS201 – 20203 | P a g emultiplexer is a 16-bit wide 4-to-1 multiplexer with 2-bit control signal,disp_sel, where 00 selects operandA for displaying, 01 selects operandB fordisplaying, 10 selects result for displaying. You can assume unused I/O pinsare connected to 0s.The calculator operations are defined by the following register transfer operations,with their corresponding control signals in Table 2.Table 2 Calculator register transfers and data flowControl signal Register transfer Commentclear Reg_A0, Reg_B0,Reg_R0, Reg_OP0 Initialise all registers to 0ld_a Reg_AKEY_IN Load operandAdisp_sel=00 DISPLAYReg_A Display operandA on 7-segld_b Reg_BKEY_IN Load operandBdisp_sel=01 DISPLAY Reg_B Display operandB on 7-segld_op Reg_OPKEY_IN Load operationld_r Reg_RReg_A op Reg_B Calculate and store result of the selectedoperation (i.e. based on op_sel value)disp_sel=10 DISPLAYReg_R Display result on 7-segPart 1: Design a datapath (1.5%)Given the available datapath components, i.e. shift register, register, arithmeticunit, and multiplexer. Design a datapath of the simple calculator as a blockdiagram. The datapath is encircled by the dashed line in the figure (next page).The datapath receives data input (i.e. numbers, operations, reset) from thekeypad and generates data output to the 7-segment displays (with the help ofinterface hardware: the keypad driver and BCD to 7-segment decoder). Dependingon the pressed key, the following single bit control inputs are also generated forthe control unit FSM:1. digit_in=1: Pressed key is a digit.2. op_in=1: Pressed key is an operation (i.e. +, -, x).3. execute_in=1: Key B (=) is pressed.4. clear_in=1: Key C is pressed.5. reset=1: Key A is pressed.Task 1: Draw your datapath design as a block diagram (i.e. show eachinternal component as a block), with clear indication of all necessary busconnections, and control signals for each component. You dont need toworry about the internal bus width.University of Auckland Lab 3 COMPSYS201 – 20204 | P a g eControl Unit FSMo p_i nld_a ld_b ld_opdigit_i nexecute_i nclear_i nFour 4-bitBCD to 7-segconvertersKeypad driverKeypadRowinputsColumnoutputsld_r disp_sel clearControl signalsreset24 4DatapathValue/OpData InputControl inputsDataOutputPart 2: Design a control unit FSM (1.5%)With the designed datapath, design a control unit FSM for it. The control unit isresponsible for coordinating the register transfer operations to achieve the overallcalculator function.Figure 2 Control Unit Finite State Machine state transition diagramFor this calculator, we have designed an incomplete FSM state transition diagram,as shown in Figure 2, where we have illustrated the conditions for the statetransitions according to the control inputs, but not the control signal outputs ineach state. The five states are:initial operandA operation operandB result RREESSEETT oopp__iinn==11 ddiiggiitt__iinn==11 eexxeeccuuttee__iinn==11cclleeaarr__iinn==11 digit_in=1, clear_in=1, execute_in=1 digit_in=1, clear_in=1, execute_in=1 op_in=1, clear_in=1, execute_in=1 op_in=1, clear_in=1, execute_in=1 digit_in=1, op_in=1, clear_in=1 digit_in=1, op_in=1, clear_in=1 digit_in=1, op_in=1, execute_in=1 digit_in=1, op_in=1, execute_in=1University of Auckland Lab 3 COMPSYS201 – 20205 | P a g e Initial – the calculator control unit FSM goes to the initial state either onpower-reset (which can happen from any state if Key A is pressed) or fromthe result state after clear command (if Key C is pressed). operandA – in which the calculator receives, stores and displays operandA. operation – in Which the operation is received and stored. operandB – in which the calculator receives, stores and displays operandB. result – in which the calculator executes the operation, stores and displaysthe result, and waits To be reinitialised.Task 2: Based on your datapath design, complete the table of controlsignals provided below, by filling in the values of the control signals in eachstate.Controlsignalstateinitial operandA operation operandB resultld_ald_bld_opld_rdisp_selclearSubmit your datapath block diagram and the table of controlsignals, as a PDF document on Canvas. The submission mustbe made before 22nd May (Friday) 11:59pm to be consideredfor marking.如有需要，请加QQ：99515681 或邮箱：99515681@qq.com

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