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EECS120A作业 写作、 辅导data课程作业、Python，Java，c++编程语言作业 写作
EECS120A Logic Design
Department of Electrical Engineering
University of California Riverside
Laboratory #2
EE 120 A
Spring 2020
LABORATORY # 2
Decoders and Muxes
PART 11
(decoder) Design of Sprinkler Valve Controller
PART 2 (multiplexer) Design of Computer Data Bus
1 Design Example guided through by TA
2
Lab 2 Decoders and Muxes
Instructors Manual
EE120A Logic Design
University of California – Riverside
Objectives
Lab 2 contains 2 parts: Part 1 guided design and Part 2 individual design.
Its purposes are to get familiar with:
1. Xilinx ISE Design software system usage.
2. Simulation and Design of controller systems based on combinational logic.
3. Generation of testbenches for logic design testing and verification.
4. Generation of waveform.
Equipment
● PC or compatible
● Xilinx ISE Design Software
● ModelSim XE III modeling software
Parts
● N/A
3
Lab 2 Decoders and Muxes
Instructors Manual
EE120A Logic Design
University of California – Riverside
PART 1. Design of a Sprinkler Valve Controller2
In this guided software experiment, we will design and test a 3 x 8 decoder (with
enable switch) for a sprinkler valve controller system:
Specification
Figure 1. Sprinkler Digital Controller System
Part A: Automatic lawn sprinkler systems control the opening and closing of water
valves. A sprinkler system must support several different zones, such as the
backyard, left side yard, right side yard, etc. Only one zones valve can be opened
at a time to maintain enough pressure in the sprinklers in that zone. In this design
assignment a sprinkler system must support up to 8 zones. Note that typically a
sprinkler system is controlled by a small microcontroller unit (MCU) which
executes a program that opens each valve only at specific times of the day and for
specific durations. However, we will limit ourselves to a sub-project that is dealing
only with opening and closing of the valves. The system must also provide a facility
to disable the opening of any valve.
Analysis and Design
Assuming a microcontroller has only four output pins a system based on a 3 x 8
decoder (with enable switch) will do the job.
2 Both parts of the lab are based on examples from Frank Vahids Digital Design
4
Lab 2 Decoders and Muxes
Instructors Manual
EE120A Logic Design
University of California – Riverside
Figure 2
MCU has one pin to indicate whether the system is active (enabled) and the other
three pins indicate the binary number of a valve to be opened. The system is a
combinational logic circuit that has 4 inputs: E (enabler) and A, B, C (the binary
value of the active zone), and 8 outputs d7, , d0 (the valve controls). The truth
table of the system is shown below.
Table 1. Truth Table of the Sprinkler System (x stands for dont care)
Following the procedure outlined in Lecture 4, Slide 13 constructing sum-ofproducts
(SOP) minterm based logic expression for each of the data outputs d.
Step 1 Capture the function
d0 = E . A . B . C
d1 = E . A . B . C
d2 = E . A . B . C
d3 = E . A . B . C
5
Lab 2 Decoders and Muxes
Instructors Manual
EE120A Logic Design
University of California – Riverside
d4 = E . A . B . C
d5 = E . A . B . C
d6 = E . A . B . C
d7 = E . A . B . C
Step 2 Convert to equations and/or minimize.
Nothing to do here (already minimized).
Step 3 Implement as a gate based logic circuit
It is shown below using a non-standard3 4-input AND gates and inverters.
3 Usage of non-standard gates largely clarifies a circuit schematic but in many cases requires a creation of a
gate library manually within Logic Design Software Environments such as Xilinx ISE Design Suite
6
Lab 2 Decoders and Muxes
Instructors Manual
EE120A Logic Design
University of California – Riverside
Figure 3. Logic Circuit Schematic of the Sprinkler System based on Table 1
Circuit Schematic Capture
Using Xilinx ISE WebPack.
File – New Project – ee120a_L2P1_sprinkler_valve_controller (or
appropriate name) – (accept defaults4 in the following pop-up hardware target wizard by4 We assume that the defaults have not changed since the settings were implemented in Lab 1. Reference
the Lab 1 settings if the default looks incorrect or unfamiliar
7
Lab 2 Decoders and Muxes
Instructors Manual
EE120A Logic Design
University of California – Riverside
pressing Next) – New Source (schematic, sprinkler_circuit) – Next –
Finish
In the middle panel window one can see a design summary tab. Switch to the
sprinkler_circuit.sch tab. This is our schematic window.
In the Symbols panel choose logic symbols for the 4-input AND gate and4 and
the invertor inv. Placing them according to the schematic5 in Figure 3 and wire
them properly with Add Wire .
Add Inputs/Outputs with Add I/O Marker.
Figure 4. Sprinkler Controller logic circuit schematic created within ISE WebPack
Lab 2 Decoders and Muxes
Instructors Manual
EE120A Logic Design
University of California – Riverside
Must be presented according to the general EE120A lab guidelines posted in iLearn.
You need to include all Verilog code you wrote for both PartA and PartB
Prelab
1. Familiarize yourself with ISE/Xilinx tutorials posted in iLearn;
2. Review relevant lecture material (e.g. decoders, muxes);
3. Try to answer all the questions and do all necessary computations in this manual
Question:
1. Write a truth table of Muxes in Part 2
2. Can you draw a schematic design for Muxes in Part 2 (not necessarily done by
Xilinx) ?
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