辅导MIPS作业、MIPS程序写作、辅导MIPS

”

Pipeline MIPS Processor
Released: Oct 10th 2019
Due: Oct 31 2019 Midnight [Instructions on how to upload your code to NYUClasses
will be provided in a separate document]
This lab is to be performed individually. We will carefully monitor all submissions
for plagiarism and any instance of plagiarism will be reported to administration.
In this Lab assignment, you will implement an cycle-accurate simulator for a 5-stage pipelined

For the purposes of this lab only, we will assume that the beq (branch-if-qual) instruction
operates like a bne (branch-if-not-equal) instruction. In other words, in your implementations you
will assume that the beq jumps to the branch address i

modification for this lab is because to implement loops we actually need the bne instruction.)
Pipeline Structure
Your MIPS pipeline has the following 5 stages:
1. Fetch (IF): fetches an instruction from instruction memory. Updates PC.
2. Decode (ID/RF): reads from the register RF and generates control signals required in
subsequent stages. In addition, branches are resolved in this stage by checking for the
branch condition and computing the effective address.
3. Execute (EX): performs an ALU operation.
4. Memory (MEM): loads or stores a 32-bit word from data memory.
5. Writeback (WB): writes back data to the RF.
Your simulator can make use of the same RF, IMEM and DMEM classes that you used for
Lab0. Complete implementations of these classes are provided for you in the skeleton code.
Note that we have not defined an ALU class since, for this lab, the ALU is simple and only
needs to perform adds and subtracts.
Each pipeline stages takes inputs from flip-flops. The input flip-flops for each pipeline stage are
described in the tables below.

2. Control Flow Hazards: You will assume that branch conditions are resolved in the
ID/RF stage of the pipeline. Your processor deals with beq instructions as follows:

b. Branch conditions are resolved in thetage. To make your life easier,
will ensure that every beq instruction has no RAW dependency with its
previous two instructions. In other words, you do NOT have to deal with
RAW hazards for branches!
c. Two operations are performed in the ID/RF stage: (i) Read_data1 and
Read_data2 are compared to determine the branch outcome; (ii) the effective
branch address is computed.
d. If the branch is NOT TAKEN, execution proceeds normally. However, if the
branch is TAKEN, the speculatively fetched instruction from PC+4 is quashed in
its ID/RF stage using the nop bit and the next instruction is fetched from the
effective branch address. Execution now proceeds normally.
The nop bit
The nop bit for any stage indicates whether it is performing a valid operation in the current clock
cycle. The nop bit for the IF stage is initialized to 0 and for all other stages is initialized to 1.
(This is because in the first clock cycle, only the IF stage performs a valid operation.)
In the absence of hazards,, the value of the nop bit for a stage in the current clock cycle is equal
to the nop bit of the prior stage in the previous clock cycle.
However, the nop bit is also used to implement stall that result from a RAW hazard or to quash
speculatively fetched instructions if the branch condition evaluates to TAKEN. See Lecture 6
slides for more details on implementing stalls and quashing instructions.
The HALT Instruction
The halt instruction is a custom instruction we introduced so you know when to stop the
simulation. When a HALT instruction is fetched in IF stage at cycle N, the nop bit of the IF stage
in the next clock cycle (cycle N+1) is set to 1 and subsequently stays at 1. The nop bit of the
ID/RF stage is set to 1 in cycle N+1 and subsequently stays at 1. The nop bit of the EX stage is
set to 1 in cycle N+2 and subsequently stays at 1. The nop bit of the MEM stage is set to 1 in
cycle N+3 and subsequently stays at 1. The nop bit of the WB stage is set to 1 in cycle N+4 and
subsequently stays at 1.
At the end of each clock cycle the simulator checks to see if the nop bit of each stage is 1. If so,
the simulation halts. Note that this logic is already implemented in the skeleton code provided to
you.
What to Output
Your simulator will output the values of all flip-flops at the end of each clock cycle. Further, when
the simulation terminates, the simulator also outputs the state of the RF and Dmem. The
skeleton code already prints out everything that your simulator needs to output. Do not modify
this code.
Testbenches and Grading
Test inputs for your simulator are in the form of imem.txt and dmem.txt files, and the
expected outputs are in the form of RFresult.txt, dmemresult.txt and stateresult.txt files.
To assist you in checking your code, we will provide sample input and output files to you.
However, your code will be graded on our own test inputs.
You are encouraged to develop your code in steps. A rough time frame for how long each step
would take is given below.
1. Step 1: your simulator should be able to handle addu, subu, lw and sw instructions
without any RAW hazards. (1 Week)
2. Step 2: in addition, your simulator should be able to handle addu, subu, lw and sw
instructions with RAW hazards. (1 Week)
3. Step 3: finally, enhance your simulator to handle beq instructions.
The grading scheme that we will use to test your code is: